// CBUS table for 168 16 MEGA BYTE SDRAM
//
0640	// cas latency
0000
0004
0642  	// Refresh period
0000
07e9
0643  	// Tras
0000
0007
0644  	// Trc
0000
000a
0645  	// Trcd
0000
0003
0646  	// Trp
0000
0003
0647  	// Trrd
0000
0002
0648  	// Trdl
0000
0001
0649  	// Txsr
0000
000a
0920
ffff
f00f
064a  	// optimize enable
0000
0001
064b  	// enable cas
0000
0000
064c	// Number of bits for SDRAM ROW address
0000
000c
064d	// Number of bits for  SDRAM BANK address
0000
0002
064e	// Number of bits for  SDRAM COLUMN address
0000
0008
064f    // MRS command: CAS = 3, burst = 7 
0000
0037
0641	// SDRAM PMI command (PMI ready will check later)
0000
0001	
000b 	// MCU Data_Delay
0000
0005
0012	// MCU slot machine selection
0000
0000
0013	// Number of slots for first slot machine
0000
0003	// Three slots (minumum possible)
0010 	// First slot machine parameters
0000
8100	// Dummy slot
0010 	// First slot machine parameters
0000
8100	// Dummy slot
0010 	// First slot machine parameters
0000
8100	// Dummy slot
0015	// MBA on/off selection
0000
0001
2064	// maximum number of cache cycles the MCU will serve in a Cache_window
0000
00ff
0641	// Wait for the MCU PMI to be ready (previouse wait command must be 1, see ROM SPEC)
0000
0001
084A	// UART Enable
0000
0001
0841	// UART interrupt mask
0000
0000
0843	// UART data format control register
0000
0083	// DLAB=1,8N1
0840	// UART clock divisor, LSB (115200)
0000
0046
0841	// UART clock divisor, MSB (115200)
0000
0000
0843	// UART data format control
0000
0003	// DLAB=0,  8N1
085A	// Modem Enable
0000
0001
0851	// Modem interrupt mask
0000
0000
0853	// Modem data format control register
0000
0083	// DLAB=1,8N1
0850	// Modem clock divisor, LSB (115200)
0000
0046
0851	// Modem clock divisor, MSB (115200)
0000
0000
0853	// Modem data format control
0000
0003	// DLAB=0,  8N1
0858
0000
0090
0859
0000
0080
0938	// Setting debounce_IRQ1 to avoid problems on certain DRAMs
0000
0010
0ff1
0000
0000
ffff
ffff
ffff
